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1What is GDS?2Recovering the circuit3Inferring the circuit Kjartan van Driel & Leander Post Per aspera ad astra Jane Street recently released a puzzle where the goal is to reverse engineer an ASIC chip, figure out what it does, and submit a solution. I urged my friend Leander to join me and see if we could figure it out. Along the way, it dawned on me that the road to the solution could be illustrated in particularly pretty terms, so here is my attempt at that. This is intended as a solution, particularly for those who read the challenge and decided they couldn't quite fit it into their schedule. It's supposed to convey the central ideas you would need to arrive at a solution. part I of three What is GDS? First, we have to open a file. Surely this is the easy bit. Two files Excluding the warmup puzzle -- which you should for sure try -- the puzzle consists of just two files: puzzle.gds and example_inputs.vcd. The puzzle centres on the Graphic Data System, or GDS file. The example inputs are there as a simple test case: one input, and the output the chip should produce for it. Layers Opening the GDS file in a dedicated program like KLayout, we can immediately see some of its structure. It describes a layout: polygons of different types, indicated by their layer. It also contains annotations, which make the entire file look like a mess when you first open it. Cells The GDS file format allows you to group polygons into cells. Such cells can be defined once and placed many times. They typically define logic gates, which in turn make up registers, computational units and so forth. Such a hierarchy makes it more manageable to design a chip. Though again, this hierarchy is typically the result of a higher-level description in Verilog, which is ultimately translated into this layout. The cell boundaries give us some of that structure to work with, even though we don't have the original Verilog. Just a layout Whilst a GDS defines a layout, on its own it says very little about what that layout actually means. Even the depiction on the right is somewhat suggestive, since we've already given the layers colours and thicknesses.
Looking at the file alone, we wouldn't know which of those layers were metal, which were silicon, or how a fab would turn them into a working chip. To make sense of them, we need to know the manufacturing process the chip was designed for. Each process has its own conventions for what the layer numbers mean. These are documented in a process design kit, or PDK, along with the rules for how the different materials can be used. So before we can read much of the circuit, we need to find out which process we're looking at. Finding the process Fortunately, the names of the logic cells give us a fairly direct clue. They start with sky130_fd_sc_hd__, which identifies a standard-cell library for the SkyWater 130 nm process. A standard-cell library is a collection of ready-made components, such as logic gates and flip-flops, that a chip designer can use without having to draw each one from transistors. The documentation for this process and library is public, so we can look up both what the layers mean and what the cells are supposed to do. Which is quite a bit more convenient than having to work all of that out from the polygons ourselves. The layers With that documentation, we can start putting names to the layers.
Near the bottom, nwell, diff and poly define the parts of the transistors. We'll look at those in a moment. Just above them is li1, short for local interconnect, which joins transistors together within a cell. Above that are five metal layers, met1 through met5, for wiring the cells together and carrying signals across the chip.
Having several layers lets wires cross without touching. To connect a wire on one layer to a wire on the next, there has to be a connection through the insulating material between them, called a via. The cut layers, the ones ending in /44, specify where those connections go. This distinction will matter when we try to follow the wires. Two polygons can overlap in the top-down view without being electrically connected, so we need to keep track of their layers as well as their shapes.
A cross-section through the layers, with connections between them. The thicknesses and spacing are adjusted to make the structure easier to see. They aren't to scale. Inputs and outputs The file also contains text labels on some of its layers. At the top level, these name the inputs and outputs of the chip, so we can already get some idea of how we're supposed to interact with it. On the left we have clk, the clock, along with rst_n, enable and I. On the right are the eight bits of O and a separate success output. The puzzle asks us to find an input that makes success go high. We don't yet know what that input should be, but at least we know where to send it and where to check the result. The pins of a cell If we zoom into one of the logic cells, we find another set of labels. These tell us where the cell's own inputs and outputs connect to the wiring around it. The cell we're looking at is an XOR gate, with two inputs, A and B, and an output, X. There are also VPWR and VGND, the power and ground connections.
These run along the top and bottom of the cell, so neighbouring cells can share them. The labels themselves are just annotations. It's the conducting material underneath each label that forms the connection. Later, we can use those positions to work out how the gates are wired together. A transistor The logic gates we've been looking at are made from transistors. For our purposes, we can think of a transistor as an electrically controlled switch: the voltage on one terminal, called the gate, determines whether current can flow between the other two, the source and drain.